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本帖最后由 Ayala 于 2017-4-22 17:27 编辑
[C] 纯文本查看 复制代码 #include <ntdef.h>
#include <ntddk.h>
char*
fmt1="PCI_COMMON_CONFIG \n\
USHORT VendorID :%04X\n\
USHORT DeviceID :%04X\n\
USHORT Command :%04X\n\
USHORT Status :%04X\n\
UCHAR RevisionID :%02X\n\
UCHAR ProgIf :%02X\n\
UCHAR SubClass :%02X\n\
UCHAR BaseClass :%02X\n\
UCHAR CacheLineSize :%02X\n\
UCHAR LatencyTimer :%02X\n\
UCHAR HeaderType :%02X\n\
UCHAR BIST :%02X\n";
char*
fmt2="\
ULONG BaseAddresses[6]:\n\
0 %08X\n\
1 %08X\n\
2 %08X\n\
3 %08X\n\
4 %08X\n\
5 %08X\n\
ULONG Reserved1[2]\n\
ULONG ROMBaseAddress:\n\
%08X\n\
ULONG Reserved2[2]\n\
UCHAR InterruptLine:\n\
%02X\n\
UCHAR InterruptPin\n\
%02X\n\
UCHAR MinimumGrant\n\
%02X\n\
UCHAR MaximumLatency\n\
%02X\n\
";
#define PCI_COMMON_CONFIG_s1(t) \
t.VendorID,\
t.DeviceID,\
t.Command,\
t.Status,\
t.RevisionID,\
t.ProgIf,\
t.SubClass,\
t.BaseClass,\
t.CacheLineSize,\
t.LatencyTimer,\
t.HeaderType,\
t.BIST
#define PCI_COMMON_CONFIG_s2(t) \
t.u.type0.BaseAddresses[0],\
t.u.type0.BaseAddresses[1],\
t.u.type0.BaseAddresses[2],\
t.u.type0.BaseAddresses[3],\
t.u.type0.BaseAddresses[4],\
t.u.type0.BaseAddresses[5],\
t.u.type0.ROMBaseAddress,\
t.u.type0.InterruptLine,\
t.u.type0.InterruptPin,\
t.u.type0.MinimumGrant,\
t.u.type0.MaximumLatency
SacnPciConfiguration()
/*
typedef struct _PCI_SLOT_NUMBER {
union {
struct {
ULONG DeviceNumber:5;
ULONG FunctionNumber:3;
ULONG Reserved:24;
} bits;
ULONG AsULONG;
} u;
} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
typedef struct _PCI_COMMON_CONFIG {
USHORT VendorID;
USHORT DeviceID;
USHORT Command;
USHORT Status;
UCHAR RevisionID;
UCHAR ProgIf;
UCHAR SubClass;
UCHAR BaseClass;
UCHAR CacheLineSize;
UCHAR LatencyTimer;
UCHAR HeaderType;
UCHAR BIST;
union {
struct {
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
ULONG Reserved1[2];
ULONG ROMBaseAddress;
ULONG Reserved2[2];
UCHAR InterruptLine;
UCHAR InterruptPin;
UCHAR MinimumGrant;
UCHAR MaximumLatency;
} type0;
} u;
UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
*/
{
PCI_SLOT_NUMBER slotData;
PCI_COMMON_CONFIG pciData;
ULONG pciBus;
ULONG slotNumber;
ULONG functionNumber;
ULONG length;
slotData.u.AsULONG = 0;
//
// Search each PCI bus.
//
for (pciBus = 0;pciBus < 256; pciBus++) {
//
// Look at each device.
//
for (slotNumber = 0;slotNumber < 32;slotNumber++) {
slotData.u.bits.DeviceNumber = slotNumber;
//
// Look at each function.
//
for (functionNumber = 0;functionNumber < 8;functionNumber++) {
slotData.u.bits.FunctionNumber = functionNumber;
/*
length = HalpPhase0GetPciDataByOffset(
pciBus,
slotData.u.AsULONG,
&pciData.ProgIf,
FIELD_OFFSET(PCI_COMMON_CONFIG,ProgIf),
sizeof(UCHAR)+sizeof(UCHAR)+sizeof(UCHAR));
*/
length = HalGetBusDataByOffset (
PCIConfiguration,
pciBus,
slotData.u.AsULONG,
&pciData.ProgIf,
FIELD_OFFSET(PCI_COMMON_CONFIG,ProgIf),
sizeof(UCHAR)+sizeof(UCHAR)+sizeof(UCHAR));
#define DbgP(f,...) DbgPrintEx(DPFLTR_SETUP_ID,DPFLTR_INFO_LEVEL,f,__VA_ARGS__)
if (length == 0) {
//DbgP("no more Slots");
break;
}
switch (pciData.BaseClass)
{
char* s;
case 1://STORAGE
switch (pciData.SubClass)
{
case 0://SCSI
s="SCSI";
break;
case 1://IDE
s="IDE";
break;
case 2://FLOPPY
s="FLOPPY";
break;
case 3://IPI
s="IPI";
break;
case 4://RAID
s="RAID";
break;
case 5://???
s="???";
break;
case 6://SATA
s="SATA";
if (pciData.ProgIf) s="SATA_AHCI";
break;
case 7://SAS
s="SAS";
break;
case 8://NVME
s="NVME";
break;
case 80://OTHER
s="OTHER";
break;
default:break;
s="????";
}
DbgP("\nSTORAGE:%s\n",s);
length = HalGetBusDataByOffset (
PCIConfiguration,
pciBus,
slotData.u.AsULONG,
&pciData,
0,
sizeof(PCI_COMMON_CONFIG));
if (length==sizeof(PCI_COMMON_CONFIG))
{
DbgP(fmt1,PCI_COMMON_CONFIG_s1(pciData));
DbgP(fmt2,PCI_COMMON_CONFIG_s2(pciData));
}
break;
case 0: //PRE_20
case 2: //NETWORK
case 3: //DISPLAY
case 4: //MULTIMEDIA
case 5: //MEMORY
case 6: //BRIDGE
case 7: //COMMUNICATION
case 8: //SYSTEM
case 9: //INPUT
case 0xA : //DOCKING
case 0xB : //PROCESSOR
case 0xC : //SERIAL
case 0xD : //WIRELESS
case 0xE : //INTELLIGENT
case 0xF : //SATELLITE
case 0x10: //CRYPT
case 0x11: //SIGNAL_PROCESSING
case 0xFF: //OTHERS
default:
break;
}
} // next PCI function
} // next PCI slot
} // next PCI bus
return 0;
} // SacnPciConfiguration()
NTSTATUS
DriverEntry(a,b)
{
SacnPciConfiguration();
return STATUS_DEVICE_CONFIGURATION_ERROR;
} |
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